| 发明名称 |
LOW POWER SCHEME TO PROTECT THE LOW VOLTAGE CAPACITORS IN HIGH VOLTAGE IO CIRCUITS |
| 摘要 |
An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode. |
| 申请公布号 |
US2015130527(A1) |
申请公布日期 |
2015.05.14 |
| 申请号 |
US201414490110 |
申请日期 |
2014.09.18 |
| 申请人 |
Texas Instruments Incorporated |
发明人 |
P Venkateswara Reddy;Ghatawade Vinayak |
| 分类号 |
H03K19/00;H03K19/003;H03K19/0185 |
主分类号 |
H03K19/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An input/output (IO) circuit comprising:
a first bias circuit and a second bias circuit coupled to a node; a first capacitor and a second capacitor being cascaded, coupled to the node, the node being defined between the first capacitor and the second capacitor; and a pad coupled to the node; wherein the first bias circuit is configured to maintain a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit is configured to maintain the voltage at the node below the threshold during the receive mode, wherein the voltage at the node is dependent on a voltage at the pad during the receive mode. |
| 地址 |
Dalllas TX US |
