发明名称 Semiconductor Device
摘要 In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.
申请公布号 US2015130022(A1) 申请公布日期 2015.05.14
申请号 US201414522481 申请日期 2014.10.23
申请人 Renesas Electronics Corporation 发明人 Watanabe Shinpei;Uchida Shinichi;Maeda Tadashi;Tanaka Shigeru
分类号 H01L49/02;H01L27/01;H04B5/00 主分类号 H01L49/02
代理机构 代理人
主权项 1. A semiconductor device comprising: a first semiconductor chip that includes a first multilayer interconnect layer and a first inductor formed in the first multilayer interconnect layer; a second semiconductor chip that includes a second multilayer interconnect layer and a second inductor formed in the second multilayer interconnect layer; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view, the first semiconductor chip includes a first non-facing region that does not face the second semiconductor chip, the second semiconductor chip includes a second non-facing region that does not face the first semiconductor chip, the first multilayer interconnect layer includes a first external connection terminal in the first non-facing region, the second multilayer interconnect layer includes a second external connection terminal in the second non-facing region, the first non-facing region, the facing region, and the second non-facing region are located in this order along a first direction, and at least one end of the first insulating film does not overlap an end of the facing region in a second direction which is a direction perpendicular to the first direction when seen from a direction perpendicular to the first semiconductor chip.
地址 Kawasaki-shi JP