METHODS OF FORMING SUBSTANTIALLY SELF-ALIGNED ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES

摘要

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

主权项

1. A method of forming a FinFET device comprising a channel region and a plurality of source/drain regions, the method comprising:
forming a first layer of a first semiconductor material on a semiconductor substrate; forming a second layer of a second semiconductor material on said first layer of said first semiconductor material, wherein said first layer of said first semiconductor material is selectively etchable relative to said semiconductor substrate and said second layer of said second semiconductor material; forming a plurality of spaced-apart trenches that extend at least partially into said semiconductor substrate, said trenches defining a fin structure for said device comprised of said first and second layers of semiconductor material, said fin structure extending in a gate-length direction across what will become said channel region and said source/drain regions for said device; forming a sacrificial gate structure above a portion of said fin structure at a location that corresponds approximately to a location of said channel region for said FinFET device; forming at least one sidewall spacer adjacent said sacrificial gate structure; performing at least one etching process to remove said sacrificial gate structure and thereby define a gate cavity; while masking portions of said fin structure positioned outside of said at least one sidewall spacer, performing at least one selective etching process through said gate cavity to selectively remove a portion of said first layer of said first semiconductor material relative to said second layer of said second semiconductor material and said substrate so as to thereby define a space between said second semiconductor material and said semiconductor substrate; filling substantially all of said space between said second semiconductor material and said semiconductor substrate with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become said channel region of said device; and after forming said substantially self-aligned channel isolation region, forming a final gate structure in said gate cavity.