| 摘要 |
In this method for manufacturing a semiconductor device, an SGT is formed on a semiconductor pillar (6) that is located on top of a semiconductor substrate (1) and wiring semiconductor layers (15, 22) are formed so as to contact side surfaces of a gate conductor layer (10d) or impurity regions (2b, 3b) that exist in the middle of the semiconductor pillar (6). First alloy layers (19a, 23a) formed on side surfaces of the wiring semiconductor layers (15, 22) connect directly to the impurity regions (2b, 3b) and the gate conductor layer (10d) and are connected to an output-wiring metal layer (Vout) via contact holes (28c, 28a) formed in the top surfaces of second alloy layers (19b, 23b) formed on the top and side surfaces of the wiring semiconductor layers (15, 22). |
