CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL)

摘要

PROBLEM TO BE SOLVED: To provide a clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver.SOLUTION: An integrated circuit (RFIC) 210 includes a PLL 240 and an analog-to-digital converter (ADC) 230. The PLL 240 receives a first clock signal CLK1 generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal CLK1 is generated by a fractional-N frequency synthesizer 260 external to the integrated circuit. The PLL 240 generates a second clock signal CLK2 with an integer divider ratio and having reduced spurs. The ADC 230 digitizes an analog baseband signal on the basis of the second clock signal CLK2 and provides digital samples. The integrated circuit 210 further includes a low noise amplifier (LNA) 222, which observes less spurs coupled via the substrate of the integrated circuit 210.