发明名称 Nonvolatile memory device, method for fabricating the same, and method for operating the same
摘要 A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a first drain selection transistor with the same structure as the memory transistors and a second drain selection transistor with the same structure as the source selection transistor. The nonvolatile memory device further includes an even drain selection line connected to the first drain selection transistors of the even strings and the second drain selection transistors of the odd strings and an odd drain selection line connected to the second drain selection transistors of the even strings and the first drain selection transistors of the odd strings.
申请公布号 US9030868(B2) 申请公布日期 2015.05.12
申请号 US201414149467 申请日期 2014.01.07
申请人 SK Hynix Inc. 发明人 Lee Nam-Jae
分类号 G11C7/00;H01L29/788;G11C16/04;G11C16/10;H01L27/115;H01L29/66 主分类号 G11C7/00
代理机构 IP & T Group LLP 代理人 IP & T Group LLP
主权项 1. A nonvolatile memory device comprising: a substrate having an active region defined by isolation layers and including a plurality of first regions which extend in one direction and second and third regions which are disposed alternately between the first regions to connect the first regions with one another; a source selection line, word lines, and first and second drain selection lines disposed over the substrate and extending to cross the first regions between the second and third regions; first and second contacts disposed over the second and third regions, respectively; and first and second wiring lines respectively connected with the first and second contacts and extending parallel to one another, wherein each of the first and second drain selection lines includes a stack structure of a tunnel dielectric layer, a floating gate, an intergate dielectric layer, and a control gate, and wherein the first drain selection line has portions of the intergate dielectric layer removed at intersections with odd-numbered first regions among the first regions, and the second drain selection line has portions of the intergate dielectric layer removed at intersections with even-numbered first regions among the first regions.
地址 Gyeonggi-do KR