Current output control device, current output control method, digitally controlled oscillator, digital PLL, frequency synthesizer, digital FLL, and semiconductor device

摘要

A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

主权项

1. A current output control device comprising:
a current cell array section including a plurality of current cell circuits that are each connected in parallel between a first terminal and a second terminal, whose ON/OFF state is switched by an input signal, that disconnect from the first terminal and the second terminal in the OFF state, that connect between the first terminal and the second terminal in the ON state so as to increase current flowing between the first terminal and the second terminal; and a code conversion section that generates signals to change a number of current cell circuits that are in the ON state according to change in an externally input code and that inputs the generated signals to the respective current cell circuits, wherein the current cell circuits in the current cell array section are arranged in an M row×N column array, wherein the code conversion section generates the signals and inputs the signals to the respective current cell circuits such that as the input code becomes active in sequence from the lowest significant bit, a specific individual number of the current cell circuits in each row are switched ON from the 1st column to the Nth column for each row in sequence from the 1st row to the Mth row, wherein the code conversion section includes a decoder section that converts the input code into row code signals for M rows and column code signals for N columns; and wherein the decoder section, as the input code becomes active in sequence from the least significant bit, increases an active number of signals by a specific number of units in sequence from the least significant bit until all are active for the column code signals of odd numbered rows, decreases an active number of signals by the specific number of units in sequence from the most significant bit for the column code of even numbered rows, and increases a number of active signals in sequence from one less significant bit for the row code when switching over from an odd numbered row to an even numbered row.