发明名称 INTERNAL JITTER TOLERANCE TESTER WITH AN INTERNAL JITTER GENERATOR
摘要 Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller.;The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.
申请公布号 US2015124861(A1) 申请公布日期 2015.05.07
申请号 US201314070249 申请日期 2013.11.01
申请人 TeraSquare Co., Ltd. ;Korea Advanced Institute of Science and Technology 发明人 BAE HyunMin;LEE Joon Yeong;PARK Jin Ho;KIM Tae Ho
分类号 H04L1/20 主分类号 H04L1/20
代理机构 代理人
主权项 1. An internal jitter tolerance tester with an internal jitter generator, the jitter tolerance tester comprising: a loop filter with a predetermined gain and a predetermined delay; an internal accumulated jitter generator to generate an accumulated jitter and output the generated accumulated jitter to a gain multiplier; the gain multiplier to be connected to an output of the loop filter and be connected to an output of the internal accumulated jitter generator; and a phase rotator controller to be connected to an output of the gain multiplier and to generate a jitter-equipped clock signal, wherein the internal accumulated jitter generator comprises, a pseudorandom binary sequence (PRBS) generator to generate 1 and −1 randomly; a subsequent accumulator to be connected to an output of the pseudorandom binary sequence generator and accumulate a random signal; a lowpass filter to be connected between the pseudorandom binary sequence generator or be connected to an output of the subsequent accumulator, the lowpass filter eliminating a high frequency spur and a quantization noise; and a gain controller to be connected to an output of the subsequent accumulator or be connected to an output of the lowpass filter, the gain controller controlling an amount of the accumulated jitter.
地址 Seoul KR