OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

摘要

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

主权项

1. A processor comprising:
a plurality of cores, each core including: a plurality of thermal sensors to provide thermal data for the core and a plurality of counters each to count a number of occurrences of an architectural event; a bus to couple the plurality of counters and the plurality of thermal sensors; and a power control unit coupled to the bus to modify a power state of one of the plurality of cores in response to an occurrence of an architectural event in the one of the plurality of cores.