| 发明名称 |
LOW LATENCY AND HIGH PERFORMANCE SYNCHRONIZATION MECHANISM AMONGST PIXEL PIPE UNITS |
| 摘要 |
A method for synchronizing a plurality of pixel processing units is disclosed. The method includes sending a first trigger to a first pixel processing unit to execute a first operation on a portion of a frame of data. The method also includes sending a second trigger to a second pixel processing unit to execute a second operation on the portion of the frame of data when the first operation has completed. The first operation has completed when the first operation reaches a sub-frame boundary. |
| 申请公布号 |
US2015123977(A1) |
申请公布日期 |
2015.05.07 |
| 申请号 |
US201314073118 |
申请日期 |
2013.11.06 |
| 申请人 |
Nvidia Corporation |
发明人 |
KANURI Mrudula;JEET Kamal |
| 分类号 |
G06T1/20 |
主分类号 |
G06T1/20 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for synchronizing a plurality of pixel processing units, the method comprising:
sending a first trigger to a first pixel processing unit to execute a first operation on a portion of a frame of data; and sending a second trigger to a second pixel processing unit to execute a second operation on the portion of the frame of data when the first operation has completed, wherein the first operation has completed when the first operation reaches a sub-frame boundary. |
| 地址 |
Santa Clara CA US |
