发明名称 新暗号規格(AES)向けの柔軟なアーキテクチャおよび命令
摘要 Methods and devices for use with the advanced encryption standard (AES) are presented including a processor comprising a decode unit to decode a single round encryption instruction to perform an AES single round encryption operation, wherein the single round encryption instruction specifies a destination register to store 128-bit input data and a source register to store a 128-bit round key; and an execution unit to execute micro-operations based on the single round encryption instruction, wherein the execution unit is to receive the 128-bit input data and the 128-bit round key, and wherein the execution unit is to perform the AES single round encryption operation on the 128-bit input data using the round key and to store 128-bit result data in the destination register.
申请公布号 JP5715218(B2) 申请公布日期 2015.05.07
申请号 JP20130222466 申请日期 2013.10.25
申请人 インテル・コーポレーション 发明人 ゲロン、シェイ;フェガリ、ワジ、ケー.;ゴーパル、ヴィノード;ラグナンダン、マカラム;ディクソン、マーティン、ジー.;チェヌパティ、スリニヴァス;クーナヴィス、マイケル、イー.
分类号 G09C1/00;G06F9/30 主分类号 G09C1/00
代理机构 代理人
主权项
地址