发明名称 Optimizations for an unbounded transactional memory (UTM) system
摘要 Disclosed is a apparatus with logic that decodes metadata access instructions, the instructions referencing the data address of a data item, and metadata logic that translates the data address to a distinct metadata address. Metadata logic also accesses the metadata referenced by the distinct metadata address in response to the decoding logic decoding the metadata instruction. Also disclosed is a program that responsive to a data access operation, which references a data address, generates a metadata access operation to reference the data address of the data address operation. The metadata access operation translating the data address to a disjoint metadata address, and accessing the metadata for the data item at the data address based on the metadata address. The metadata access instruction may be a metadata bit test and set instruction, metadata store and set instruction, a metadata store and reset instruction, a compressed metadata test instruction, a compressed metadata store instruction or a compresses metadata clear instruction.
申请公布号 GB2519877(A) 申请公布日期 2015.05.06
申请号 GB20150000492 申请日期 2009.06.26
申请人 INTEL CORPORATION 发明人 GAD SHEAFFER;JAN GRAY;BURTON SMITH;ALI-REZA ADL-TABATABAI;ROBERT GEVA;VADIM BASSIN;DAVID CALLAHAN;YANG NI;BRATIN SAHA;MARTIN TAILLEFER;SHLOMO RAIKIN;KOICHI YAMADA;LANDY WANG;ARUN KISHAN
分类号 G06F9/30;G06F9/318;G06F12/10 主分类号 G06F9/30
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