发明名称 Clock recovery circuit for a receiver using a decision-feedback equalizer
摘要 A signal equalization method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more than one fourth of a data rate for the transmitted data; generating by the phase-error detector a phase-error level based on the detected phase errors; and recovering, by a clock-recovery circuit for the DFE and the phase-error detector, a clock signal associated with the transmitted data based on the phase error level.
申请公布号 EP2487850(A3) 申请公布日期 2015.05.06
申请号 EP20120155064 申请日期 2012.02.13
申请人 FUJITSU LIMITED 发明人 HIDAKA, YASUO
分类号 H04L25/03;H04L7/033 主分类号 H04L25/03
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