Dynamic cascode-managed high-voltage word-line driver circuit

摘要

A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

主权项

1. A dynamic logic driver circuit for generating a buffered global word-line output signal having a voltage swing substantially greater than a voltage swing of an input signal provided to the dynamic logic driver circuit, the dynamic logic driver circuit comprising:
an input for receiving the input signal; an input logic stack comprising a first plurality of transistors having source and drain terminals connected in series between a power supply voltage and a power supply return voltage, wherein a connection between two of the first plurality of transistors is further connected to an evaluation node, wherein a first one of the first plurality of transistors has a gate coupled to a pre-charge signal and a source coupled to the evaluation node for pre-charging the evaluation node in response to the pre-charge signal, wherein a second one of the first plurality of transistors has a gate terminal connected to the input, wherein at least a third one of the first plurality of transistors is biased by at least one reference voltage, and wherein the reference voltage is between the power supply voltage and the power supply return voltage, so that the third transistor forms a cascode follower that prevents a leakage current within the input logic stack from causing a full difference between the power supply voltage and the power supply return voltage from being applied across a given one of the first transistor or the second transistor; and an output driver circuit for generating the buffered global word-line output signal from a state of the evaluation node.