| 发明名称 | Input buffer circuit | ||
| 摘要 | There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different. | ||
| 申请公布号 | US9024653(B2) | 申请公布日期 | 2015.05.05 |
| 申请号 | US201313840510 | 申请日期 | 2013.03.15 |
| 申请人 | Samsung Electro-Mechanics Co., Ltd. | 发明人 | Kim Dong Hwan;Pang Sung Man |
| 分类号 | H03K17/16;H03K19/0948 | 主分类号 | H03K17/16 |
| 代理机构 | McDermott Will & Emery LLP | 代理人 | McDermott Will & Emery LLP |
| 主权项 | 1. An input buffer circuit comprising: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, reference levels of the first and second operating units determining a high or low level of the input signal being set to be different. | ||
| 地址 | Suwon, Gyunggi-Do KR | ||