Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout

摘要

Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

主权项

1. A computer-implemented method for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout, the method comprising:
mapping, by using a computer, a plurality of violations of the integrated circuit design layout to a graph; partitioning the graph into a plurality of sub-graphs, wherein each of the plurality of sub-graphs include a plurality of edges and a plurality of nodes, wherein at least one set of the plurality of nodes are collapsible into a single node to enable more accurate inspection of an individual loop; detecting a plurality of odd loops in each of the plurality of sub-graphs; and visualizing the plurality of odd loops in both at least one of the plurality of sub-graphs and a corresponding integrated circuit design layout.