METHOD FOR INCREASING THE INTEGRATION LEVEL OF SUPERCONDUCTING ELECTRONICS CIRCUITS, AND A RESULTING CIRCUIT

摘要

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

主权项

1. A planarized integrated circuit on a substrate, comprising:
a series of planarized layers formed successively on the substrate, each respective layer comprising:
an electrically conductive layer;an electrically conductive via layer adjacent to the electrically conductive layer;wherein the electrically conductive via layer adjacent to the electrically conductive layer is patterned into a set of vias which define a set of vertically extending structures which electrically interconnect with conductive structures of an adjacent layer, and the electrically conductive layer is patterned into a set of wires by removal of the surrounding portions of the electrically conductive layer, with the set of vertically extending structures extending above the set of wires; anda planarized insulating layer formed over the set of wires and the set of vias, such that upper portions of the set of vertically extending structures are exposed through the planarized insulating layer.