发明名称 MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) CROSS-TIER CLOCK SKEW MANAGEMENT SYSTEMS, METHODS AND RELATED COMPONENTS
摘要 Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.
申请公布号 US2015121327(A1) 申请公布日期 2015.04.30
申请号 US201414159028 申请日期 2014.01.20
申请人 QUALCOMM Incorporated 发明人 Kamal Pratyush;Du Yang
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A monolithic three dimensional (3D) integrated circuit (IC) (3DIC) clock tree, comprising: at least one first clock branch of the clock tree disposed in a first 3DIC tier, the at least one first clock branch comprising a first single programmable delay cell configured to receive a clock signal and generate a first delay output comprised of a first delayed clock signal based on a first control input; at least one second clock branch of the clock tree disposed in a second 3DIC tier, the at least one second clock branch comprising a second single programmable delay cell configured to generate a second delay output comprised of a second delayed clock signal based on a second control input, and a delay sense circuit positioned in at least one of the first 3DIC tier and the second 3DIC tier, the delay sense circuit comprising a first delay input coupled to the first delay output and a second delay input coupled to the second delay output, the delay sense circuit configured to generate a control input based on the difference in time arrival between the first delay input and the second delay output.
地址 San Diego CA US