Techniques for providing a semiconductor memory device

摘要

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

主权项

1. A method for biasing a semiconductor memory device comprising the steps of:
applying a first voltage potential to a first region of a first memory cell in an array of memory cells via a respective source line of the array; applying a second voltage potential to a second region of the first memory cell via a respective bit line of the array; applying a third voltage potential to a body region of the first memory cell via at least one respective word line of the array that is capacitively coupled to the body region; and applying a fourth voltage potential to a third region of the first memory cell via a respective carrier injection line of the array; wherein the first region, the second region, and the body region have a common first doping polarity.