Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells

摘要

A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors and a plurality of odd pass transistors. Each of the even pass transistors has a, control terminal coupled to a respective one of a plurality of even selection lines, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to an even global bit line. Each of the odd pass transistors has a control terminal coupled to a respective one of a plurality of odd selection lines, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to an odd global bit line.

主权项

1. A memory device, comprising:
a memory cell array, comprising a plurality of even local bit lines and a plurality of odd local bit lines; and a column decoder, comprising:
a plurality of even pass transistors, wherein each of the even pass transistors has a control terminal coupled to a respective one of a plurality of even selection lines, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to an even global bit line; anda plurality of odd pass transistors, wherein each of the odd pass transistors has a control terminal coupled to a respective one of a plurality of odd selection lines, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to an odd global bit line; wherein the even global bit line is different from the odd global bit line; and wherein when one of the even pass transistors is selected and enabled, the other unselected even pass transistors are disabled, and all of the odd pass transistors are enabled.