Static random access memory (SRAM) global bitline circuits for reducing power glitches during memory read accesses, and related methods and systems

摘要

Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.

主权项

1. A static random access memory (SRAM) global bitline circuit for a plurality of SRAM bitcells, comprising:
a global bitline enable generation circuit configured to generate a global bitline enable in response to a falling transition of a system clock; and a bitline evaluation circuit coupled to an aggregated read bitline configured to receive data stored in a selected SRAM bitcell among a plurality of SRAM bitcells of an SRAM data array, the bitline evaluation circuit configured to:
receive the data from the selected SRAM bitcell on the aggregated read bitline; andgenerate a global bitline provided as an SRAM data for the SRAM data array containing the data in response to the global bitline enable.