Semiconductor device

摘要

Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

主权项

1. A semiconductor device comprising:
a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected, wherein the circuit board comprises:
an insulation layer comprising a center region and peripheral regions around the center region;a plurality of center circuit patterns formed in the center region of the insulation layer;a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer; anda protection layer,wherein the center circuit patterns are wider than the peripheral circuit patterns, andwherein the peripheral circuit patterns comprise:
first-direction peripheral circuit patterns disposed in mutually-facing first peripheral regions and running parallel with a first direction, wherein a respective exposed portion of each of the first-direction peripheral circuit patterns is exposed through a respective opening in the protection layer and runs parallel with the first direction; andsecond-direction peripheral circuit patterns disposed in mutually-facing second peripheral regions different from the first peripheral regions, the second-direction peripheral circuit patterns running parallel with a second direction different from the first direction, wherein a respective exposed portion of each of the second-direction peripheral circuit patterns is exposed through a respective opening in the protection layer and runs parallel with the second direction.