发明名称 |
Semiconductor structure and method of forming the same |
摘要 |
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode. |
申请公布号 |
US9018677(B2) |
申请公布日期 |
2015.04.28 |
申请号 |
US201113270502 |
申请日期 |
2011.10.11 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Yao Fu-Wei;Hsu Chun-Wei;Yu Chen-Ju;Yu Jiun-Lei Jerry;Yang Fu-Chih;Hsiung Chih-Wen |
分类号 |
H01L29/66;H01L31/06;H01L31/0256;H01L21/338;H01L21/02;H01L29/778;H01L29/20 |
主分类号 |
H01L29/66 |
代理机构 |
Lowe Hauptman & Ham, LLP |
代理人 |
Lowe Hauptman & Ham, LLP |
主权项 |
1. A semiconductor structure comprising:
a first III-V compound layer; a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer; a dielectric cap layer over the second III-V compound layer; a source feature and a drain feature disposed on a top surface of the second III-V compound layer; a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature; a carrier channel depleting layer disposed on the second III-V compound layer, wherein a portion of the carrier channel depleting layer is under at least a portion of the gate electrode; and a protection layer over the dielectric cap layer and over the source feature and contacting a sidewall surface of the source feature farthest from the gate electrode and over the drain feature and contacting a sidewall surface of the drain feature farthest from the gate electrode, wherein the carrier channel depleting layer extends over the protection layer. |
地址 |
TW |