Non-volatile memory apparatus and data verification method thereof

摘要

A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.

主权项

1. A non-volatile memory apparatus, comprising:
a plurality of memory cells; a page buffer, coupled to the memory cells, storing a plurality of buffered data and programming the plurality of memory cells according to the plurality of buffered data; a sense amplifier, sensing data read from the memory cells for generating a read-out data; a write circuit, coupled to the page buffer, receiving a program data or a rewrite-in data and writing the program data or the rewrite-in data to the page buffer to be one of the buffered data; and a sense and compare circuit, coupled to the page buffer and the write circuit, reading the buffered data, and comparing the read-out data and the buffered data to generate a compared result, wherein, the sense and compare circuit determines the rewrite-in data to be the program data or an inhibiting data according to the compared result, wherein the page buffer comprises:
a tri-state inverter, has an input end and an output end, the tri-state inverter is controlled by a latch enable signal;an inverter, has an input end and an output end, the input end of the inverter is coupled to the output end of the tri-state inverter, the output end of the inverter is coupled to the input end of the tri-state inverter; anda transmission gate, coupled between the write circuit and the output end of the tri-state inverter, the transmission gate is controlled by a read-write latch signal and a write latch signal to be turned on or off.