| 摘要 |
The invention relates to a digital sensing circuit (100) for a secondary clock signal (204) to be monitored for clock failure with the aid of a primary clock signal (202), comprising a flip-flop (102) which has a clock input (108), a data input (106), a Q output (110) and a reset input (112), and further comprising an n-bit counter (104) which has a clock input (114), a reset input (128) and a counter reading output (116). The digital sensing circuit according to the invention should avoid meta-stable states being reached and also detect multiple state changes of the secondary clock signal (204) within a cycle time and thus be suitable for operating safety-relevant assemblies, which can also be used in nuclear power plants. For this purpose, the flip-flop (102) and the n-bit counter (104) are wired electrically to each other, wherein n >= 2, the primary clock signal (202) is present on the clock input (114) of the n-bit counter (104), the secondary clock signal (204) is present on the clock input (108) of the flip-flop (102), a constant signal is present on the data input (106) of the flip-flop (102), the Q output (110) of the flip-flop (102) is connected to the reset input (128) of the n-bit counter (104), and the counter reading output (116) of the n-bit counter (104) is connected to the reset input (112) of the flip-flop (102) via an interposed logic gate (122). |
