Reducing warpage for fan-out wafer level packaging

摘要

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

主权项

1. A method, comprising:
packaging an integrated circuit die, the integrated circuit die having an active surface and an inactive surface that is substantially parallel to the active surface and a plurality of sides that extend between the active surface and the inactive surface, the packaging including:
positioning the active surface of the integrated circuit die on a first surface;positioning the inactive surface of the integrated circuit die in an encapsulant in a mold chamber;covering only the plurality of sides of the integrated circuit die with the encapsulant by compressing the first surface towards the encapsulant in the mold chamber; andpreventing the encapsulant from covering the inactive surface and the active surface of the integrated circuit die by compressing the inactive surface of the integrated circuit die into a resilient surface in the mold chamber.