Error detection correction method and semiconductor memory apparatus

摘要

In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability α from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating reliability β from a bit node to a plurality of check nodes connected to the bit node, the check node includes a parity of two bits or more.

主权项

1. An error detection correction method, comprising:
performing decoding processing using a sum-product algorithm, which repeats processing of propagating a reliability α from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating a reliability β from a bit node to a plurality of check nodes connected to the bit node, wherein the check node includes a parity of two bits or more.