| 摘要 |
<p>Frequency and Phase locked Loops for controlling the frequency and phase of an output signal in response to an input Ref(t) signal, comprising a frequency control loop for controlling the frequency of an output signal in response to an input signal Ref(t) frequency according to frequency error between its output signal and input signal, a phase control loop for controlling the phase of an output signal to match with an input signal phase according to the first static phase error between its output signal and input signal Ref(t) and to the phase error between the first static phase error and the subsequent static phase error, means for using the first static phase error of Er2 value as a reference phase error to compare with subsequent Er2 to add or subtract phase delay to output signalgenerated by the frequency control loop and output a frequency and phase locked output signal out(t).</p> |
