Write transaction management within a memory interconnect

摘要

A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty. A first write transaction is sent to the shared memory. When and if any cached line of data is received from the further transaction masters, then the portion data is used to form a second write transaction which is sent to the shared memory and writes the remaining portions of the cached line of data which were not written by the first write transaction in to the shared memory. The serialization circuitry stalls any transaction requests to the write line of data until the first write transaction.

主权项

1. A memory interconnect apparatus for connecting an external shared memory with a first transaction master and a second transaction master, at least said second transaction master including a local cache memory, said memory interconnect apparatus comprising:
write control circuitry configured to respond to a write unique transaction received from said first transaction master to write data from one or more selected portions of a write line of data to said shared memory by: (i) storing portion data identifying said one or more selected portions within said write line of data; (ii) sending a first snoop request to said second transaction master requesting, if said local cache of said second transaction master is storing a cached line of data corresponding to said write line of data within said shared memory, said second transaction master to invalidate said cached line of data within said local cache and to send said cached line of data to said write control circuitry; (iii) sending to said shared memory a first write transaction for writing into said shared memory at least said data from said one or more selected portions of said write line of data without waiting for any said cached line of data to be received from said second transaction master; and (iv) when said cached line of data is received from said second transaction master, using said portion data to identify one or more remaining portions of said cached line of data that do not correspond to said one or more selected portions within said write line of data and sending to said shared memory a second write transaction for writing into said shared memory data from said one or more remaining portions of said cached line of data but not data from said cached line of data corresponding to said one or more selected portions of said write line of data; and serialisation circuitry coupled to said write control circuitry and configured to stall any transaction requests to said shared memory corresponding to said write line of data until said first write transaction, any invalidation of said cached line of data and any said second write transaction are indicated as completed.