| 主权项 |
1. An integrated circuit active memory device comprising:
a memory device having a data bus containing a plurality of data bus bits; an array of processing elements each of which is coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements; register files coupled to the array of processing elements and the memory device, the register files transferring data between the processing elements and the memory device; a host interface port coupled to the memory device and operable to receive direct access memory commands to provide direct access to the memory device to transfer compressed data to and from the memory device; a task buffer coupled to a command engine and a memory controller, the task buffer operable to receive high level task commands from the memory controller and provide the high level commands to the command engine in an order received, wherein the high level task commands include a task address; the command engine coupled to receive task commands from the task buffer and operable to generate corresponding sequences of processing element instructions and memory instructions responsive to respective task commands to control the operation of the memory device and the processing elements to generate corresponding sequences of instructions to read data from and write data to the memory device, at least some of the instructions generated by the command engine responsive to the task commands causing the processing elements to decompress compressed data transferred to the active memory device through the host interface port and store the decompressed data in the memory device or to compress decompressed data transferred from the memory device that is to be transferred from the active memory device through the host interface port; a processing element instructions buffer coupled to the command engine and an array control unit, the processing element instructions buffer operable to receive sequences of processing element instructions from the command engine and provide the sequences of processing element instructions to the array control unit in an order received; the array control unit coupled to the processing element instructions buffer and the processing elements, the array control unit being operable to receive the sequences of processing element instructions from the processing element instructions buffer and to generate array control unit microinstructions responsive to the sequences of processing element instructions received from the processing element instructions buffer, at least some of the microinstructions causing the processing elements to either decompress data transferred to the active memory device through the host interface port and then store the decompressed data in the memory device or to compress decompressed data transferred from the memory device that is to be transferred through the host interface port; a memory instructions buffer coupled to the command engine and a memory device control unit, the memory instructions buffer operable to receive sequences of memory instructions from the command engine and provide the sequences of memory instructions to the memory device in an order received; and the memory device control unit coupled to the memory instructions buffer and the memory device, the memory device control unit operable to receive the sequences of memory instructions from the memory instructions buffer and to generate memory commands responsive to the sequences of memory instructions received from the memory instructions buffer. |
