发明名称 |
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING AND INSPECTING APPARATUS, AND INSPECTING APPARATUS |
摘要 |
A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher. |
申请公布号 |
US2015104889(A1) |
申请公布日期 |
2015.04.16 |
申请号 |
US201414579968 |
申请日期 |
2014.12.22 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
KATO Takahiko;NAKANO Hiroshi;AKAHOSHI Haruo;TAKADA Yuuji;SUDO Yoshimi;FUJIWARA Tetsuo;KANNO Itaru;SHONO Tomoryo;HIROSE Yukinori |
分类号 |
H01L21/66;H01L23/532;H01L21/768 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
1. A method of manufacturing a semiconductor device comprising the steps of: forming an insulating layer on a semiconductor substrate; and forming at least one layer of Cu wiring in the insulating layer via a composite layer including a barrier layer and a seed layer on the barrier layer and provided between the Cu wiring and the insulating layer, wherein,
a step of examining grain boundary characteristics of the Cu wiring is provided after the step of forming the Cu wiring. |
地址 |
Kawasaki-shi JP |