| 摘要 |
In a high side region (10), the surface layer of a p---type substrate (1) is provided with a 1n-th diffusion region (2) having formed therein a PMOS (20) constituting a gate driver circuit, and a 2n-th diffusion region (3) having formed in an interior portion thereof a p diffusion region (4). The p diffusion region (4) has formed therein an NMOS (40) constituting a gate driver circuit. A p isolation diffusion region (5) at ground potential is provided between the 1n-th diffusion region (2) and the 2n-th diffusion region (3), and the 1n-th diffusion region (2) and the 2n-th diffusion region (3) are electrically separated from each other. The 1n-th diffusion region (2) is connected to a VB terminal at power source potential (VB). The 2n-th diffusion region (3) is connected to a terminal (30) at reference potential (VS) or floating potential. The p diffusion region (4) is connected to a VS terminal at reference potential. It is thereby possible to mitigate parasitic operation resulting from surges without the use of external parts, and to prevent the elements from being damaged. |
