ADDRESS GENERATION IN A DATA PROCESSING APPARATUS

摘要

A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

主权项

1. A data processing apparatus comprising:
processing circuitry for processing data; an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said data processing; wherein said program instructions comprise an address calculating instruction having an instruction size, said processing circuitry being responsive to said address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value, said partial address result specifying a portion of a full address specifying a memory location of an information entity, wherein said partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction.