Clock generating circuit, semiconductor device including the same, and data processing system

摘要

A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a first operation mode in which a phase of the internal clock signal is changed in synchronization with a sampling clock signal and a second operation mode in which the phase of the internal clock signal is fixed. The mode switching circuit shifts the phase-controlling unit to the first operation mode in response to a trigger signal, such as a refresh signal, and, shifts the phase-controlling unit to the second operation mode in a state where the internal clock signal attains a predetermined phase.

主权项

1. A semiconductor device, comprising:
a clock generating circuit that generates an internal clock signal based on an external clock signal, wherein the clock generating circuit includes:
a clock generating unit that generates the internal clock signal;a phase-controlling unit that controls the clock generating unit by using a phase control value so as to adjust a phase of the internal clock signal to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal; anda mode switching unit that switches an operation mode of the phase-controlling unit, wherein the phase-controlling unit includes a frequency dividing circuit that divides the external clock signal to generate a divided clock signal, the phase control value being updated in response to the divided clock signal, wherein the phase-controlling unit has a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, wherein the mode switching unit is responsive to a trigger signal to cause the phase-controlling unit to transition from the second operation mode to the first operation mode, and the mode switching unit changes the phase-controlling unit from the first operation mode to the second operation mode in response to a state where the internal clock signal attains a predetermined phase, and wherein the trigger signal is generated in response to an output signal of a power detecting circuit of the semiconductor device.