发明名称 Forming arsenide-based complementary logic on a single substrate
摘要 In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.
申请公布号 US9006707(B2) 申请公布日期 2015.04.14
申请号 US200711712191 申请日期 2007.02.28
申请人 Intel Corporation 发明人 Hudait Mantu K.;Kavalieros Jack T.;Datta Suman;Radosavljevic Marko
分类号 H01L29/06;H01L21/8238;H01L21/8252;B82Y10/00;H01L21/8258;H01L27/06;H01L29/04 主分类号 H01L29/06
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. An apparatus comprising: a silicon (Si) substrate; an n-type semiconductor device formed over the SI substrate from a stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer; a p-type semiconductor device formed over the Si substrate from a stack including the first buffer layer, the second buffer layer formed over the first buffer layer, a second device layer formed over the second buffer layer; and an isolation interposed between the n-type semiconductor device and the p-type semiconductor device; wherein the first device layer comprises: a lower barrier layer that is inverse step graded within the lower barrier layer itself, the lower barrier layer comprising one of the indium aluminium arsenide (InxAl1-xAs) an indium gallium aluminium arsenide (InGaAlAs); anda quantum well layer, formed over the lower barrier layer, comprising indium gallium arsenide (InxGa1-xAs).
地址 Santa Clara CA US