Nonvolatile memory with split substrate select gates and hierarchical bitline configuration

摘要

Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

主权项

1. A non-volatile memory comprising:
at least two groups of non-volatile memory cells each eraseable in an erase operation; local bitlines coupled to the non-volatile memory cells of each group of the at least two groups; a global bitline; and a plurality of select devices corresponding to a group of the at least two groups, the plurality of select devices configured to disconnect all the local bitlines of the group from the global bitline, wherein each of the plurality of select devices corresponding to the group are disabled in response to receiving a local bitline select signal.