DIE TESTING USING TOP SURFACE TEST PADS

摘要

Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

主权项

1. A die of semiconductor material comprising:
A. functional die pads formed at the periphery of the die; B. test die pads separate from the functional die pads; C. functional circuitry having functional input terminals, functional output terminals, and an enable input; D. a functional input buffer having an input coupled with a functional die pad and an output coupled with a functional input terminal; E. a test circuit output buffer having an input coupled with an output terminal that is not coupled with a functional die pad, an output that is coupled with a test die pad, and an enable input; and F. an enable input buffer having an input coupled with an enable test die pad, and an output coupled with the enable input of the functional circuitry and with the enable input of the test circuit output buffer.