| 发明名称 |
COMMON WELL BIAS DESIGN FOR A DRIVING CIRCUIT AND METHOD OF USING SAME |
| 摘要 |
A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well. |
| 申请公布号 |
US2015097597(A1) |
申请公布日期 |
2015.04.09 |
| 申请号 |
US201414566061 |
申请日期 |
2014.12.10 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN Chia-Hui;CHEN Yu-Ren |
| 分类号 |
G05F3/16 |
主分类号 |
G05F3/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A driving circuit comprising:
a common well; a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well; and a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well. |
| 地址 |
Hsinchu TW |
