发明名称 Verification of design derived from power intent
摘要 An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.
申请公布号 US9002694(B2) 申请公布日期 2015.04.07
申请号 US201213463034 申请日期 2012.05.03
申请人 Freescale Semiconductors, Inc. 发明人 Feng Xiushan;Bhadra Jayanta;Little Scott R.
分类号 G06F17/50;G06F1/32 主分类号 G06F17/50
代理机构 VanLeeuwen & VanLeeuwen 代理人 VanLeeuwen & VanLeeuwen ;Geld Jonathan N.
主权项 1. A method comprising: generating a power state graph based upon power intent data of a power design, wherein the power state graph comprises a plurality of edges based upon a plurality of power mode transition conditions included in the power intent data to transition between one or more of a plurality of power modes of the power design; updating the power intent data to include one or more new power mode transition conditions in response to determining that a transition sequence comprising one or more of the plurality of edges fails to exist in the power state graph from a selected first power mode to a selected second power mode, the selected first power mode and the selected second power mode included in the plurality of power modes; generating an updated power state graph based upon the updated power intent data; generating simulation stimuli based upon the updated power state graph; and simulating the power design utilizing the generated simulation stimuli.
地址 Austin TX US