发明名称 |
Blocking current leakage in a memory array |
摘要 |
A method for blocking current leakage through defective memory cells in a memory array is provided. The memory cells include access devices and programmable resistance memory elements. The method includes identifying addresses of defective memory cells in the memory array, and applying a modifying bias condition to modify the defective memory cells at the identified addresses. The modifying bias condition causes the defective memory cells to transform into a current blocking condition. The method also includes storing the identified addresses in a redundancy table of addresses. An automatic test system includes a device tester adapted to identify addresses of defective memory cells in a memory array in an integrated circuit under test, and to apply a modifying bias condition to modify the defective memory cells at the identified addresses. |
申请公布号 |
US9001550(B2) |
申请公布日期 |
2015.04.07 |
申请号 |
US201213458644 |
申请日期 |
2012.04.27 |
申请人 |
Macronix International Co., Ltd. |
发明人 |
Lung Hsiang-Lan |
分类号 |
G11C11/00;H01L45/00;G11C17/06;G11C29/00;G11C13/00;G11C29/08;G11C29/44 |
主分类号 |
G11C11/00 |
代理机构 |
Haynes Beffel & Wolfeld LLP |
代理人 |
Haynes Beffel & Wolfeld LLP |
主权项 |
1. A method for blocking current leakage through defective memory cells in a memory array, the memory cells including access devices and programmable resistance memory elements, comprising:
identifying addresses of defective memory cells in the memory array; and applying a modifying bias condition to modify programmable resistance memory elements in the defective memory cells at the identified addresses, forming modified defective memory cells having a current blocking condition under bias conditions applied during operation of the array, wherein the modifying bias condition is different from the bias conditions. |
地址 |
Hsinchu TW |