发明名称 NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY
摘要 A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.
申请公布号 US2015091079(A1) 申请公布日期 2015.04.02
申请号 US201314041647 申请日期 2013.09.30
申请人 Freescale Semiconductor, Inc. 发明人 PERERA ASANGA H.;Hong Cheong Min;Kang Sung-Taeg;Yater Jane A.
分类号 H01L27/115 主分类号 H01L27/115
代理机构 代理人
主权项 1. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion and a logic portion, comprising: forming a select gate over the substrate in the NVM portion and a first protection layer over the logic portion; forming a control gate and a charge storage layer over the substrate in the NVM portion, wherein a top surface of the control gate is substantially coplanar with a top surface of the select gate and the charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, is partially over the top surface of the select gate; forming a second protection layer over the NVM portion and the logic portion; removing the second protection layer and the first protection layer from the logic portion leaving a portion of the second protection layer over the control gate and the select gate; and forming a gate structure over the logic portion comprising a gate dielectric of high k material and a metal gate over the gate dielectric.
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