| 主权项 |
1. A memory, comprising:
a plurality of memory cells; and an input/output circuit coupled to the plurality of memory cells, and configured to drive data from at least one of the plurality of memory cells onto a data node, the input/output circuit comprising:
a plurality of pull-up transistors coupled between a first node and the data node;a plurality of pull-up circuits configured to receive a data signal, each of the plurality of pull-up circuits including a transistor configured to provide the data signal to a latch responsive to a respective timing signal and wherein each pull-up circuit of the plurality of pull-up circuits is further configured to provide a respective control signal from the latch to a gate of a respective pull-up transistor of the plurality of pull-up transistors responsive to the data signal and the respective timing signal, wherein the respective pull-up transistor is configured to switch responsive to the respective control signal; anda plurality of timing circuits coupled to the plurality of pull-up circuits, each of the plurality of timing circuits configured to provide the respective timing signal to a respective one of the plurality of pull-up circuits, and wherein the plurality of timing circuits are configured to provide the timing signals to cause the plurality of pull-up circuits to provide the respective control signals to switch the pull-up transistors at different times to modulate a slew rate of a signal on the data node. |
