OPTIMIZATION OF INSTRUCTIONS TO REDUCE MEMORY ACCESS VIOLATIONS

摘要

Mechanisms for reducing memory access violations are disclosed. Sets of instructions may be identified and the identified sets of instructions may be re-translated or optimized to generate other sets of instructions. Execution of the other sets of instructions is analyzed to determine whether additional memory access violations occur. When additional memory access violations occur, further sets of instructions may be generated or re-translation/optimization of instructions may be disabled.

主权项

1. An apparatus comprising:
a memory module to store a plurality of instructions of an application; a processor communicatively coupled to the memory, the processor to:
identify a first set of instructions from the plurality of instructions, wherein execution of the first set of instructions is to cause a first memory dependence violation;generate a second set of instructions;replace the first set of instructions with the second set of instructions at a same location in the plurality of instructions as the first set of instructions;determine that execution of the second set of instructions is to cause a second memory dependence violation; andreplace the second set of instructions with the first set of instructions or generate a third set of instructions.