VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS

摘要

In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed.

主权项

1. An apparatus comprising:
a controller in communication with a first non-volatile memory device, the first non-volatile memory device comprising a first array of non-volatile memory cells configured to store data, a first register comprising volatile memory, and a second register comprising volatile memory, wherein the controller is configured to generate commands to cause the first non-volatile memory to:
load data to be programmed to the first array of non-volatile memory cells to the first register;load data read from the first array of non-volatile memory cells to the second register; andprovide data from the second register to the controller while the first register is holding the data to be programmed to the first array of non-volatile memory cells.