Contact resistance reduction employing germanium overlayer pre-contact metalization

摘要

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

主权项

1. A transistor device, comprising:
a substrate having a channel region; a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region; source and drain regions in the substrate and adjacent to the channel region; a dielectric over the substrate, the dielectric having a contact trench formed over at least one of the source and drain regions; a boron doped germanium layer entirely within the contact trench and on at least a portion of the source and drain regions, the boron doped germanium layer comprising a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm−3; and a metal-germanide contact on the boron doped germanium layer.