Semiconductor integrated circuit with TSV bumps

摘要

A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other.

主权项

1. A semiconductor integrated circuit, comprising:
a plurality of through silicon via (TSV) bumps; a plurality of input/output (I/O) buffers connected to said plurality of TSV bumps, respectively; and first and second main power lines, wherein said plurality of I/O buffers respectively include a plurality of electrostatic discharge (ESD) protection circuitries, wherein each of said ESD protection circuitries includes: a P-channel ESD protection circuitry; and an N-channel ESD protection circuitry, wherein said first main power lines supply a first voltage to a plurality of said P-channel ESD protection circuitries, wherein said second main power lines supply a second voltage to a plurality of said N-channel ESD protection circuitries; wherein said plurality of TSV bumps are arrayed in a matrix and arranged spaced apart at predetermined intervals in each of first and second directions defined in said matrix, wherein each of said plurality of ESD protection circuitries is disposed between two of said plurality of TSV bumps, said two being arranged adjacent to each other in said first or second direction, wherein said first main power lines are disposed to overlap said plurality of P-channel ESD protection circuitries, wherein said second main power lines are disposed to overlap said plurality of N-channel ESD protection circuitries, and wherein said first and second main power lines are arranged orthogonally to each other.