Semiconductor device, image display device, storage device, and electronic device

摘要

A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.

主权项

1. A semiconductor device comprising:
a first circuit comprising a first transistor; and a second circuit electrically connected to a gate of the first transistor through a first signal line, the second circuit comprising:
first to n-th inverters being sequentially connected in series, wherein n is a natural number larger than one;a bootstrap circuit; anda delay circuit, wherein an input terminal of the first inverter is electrically connected to a wiring to which a selection signal is input, wherein an output terminal of the n-th inverter is electrically connected to the first signal line, wherein high-potential input terminals of the first to (n−1)th inverters are electrically connected to a second signal line to which a first potential is input, wherein low-potential input terminals of the first to n-th inverters are electrically connected to a third signal line to which a second potential lower than the first potential is input, wherein the delay circuit is configured to output a delay signal to the bootstrap circuit so as to start boosting by the bootstrap circuit at a timing later than a timing that the selection signal is input to the input terminal of the first inverter, and wherein the bootstrap circuit is configured to output a third potential higher than the first potential to a high-potential input terminal of the n-th inverter in response to the delay signal.