| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generation circuit that effectively reduces EMI.SOLUTION: The present invention is the clock generation circuit including a modulation control circuit for performing a predetermined frequency modulation on a clock signal generated by a PLL circuit. The PLL circuit includes: a first oscillation circuit for generating a reference signal; a first frequency division circuit for frequency-dividing the reference signal according to a first frequency division ratio; a second oscillation circuit for generating a clock signal of a predetermined frequency according to a given phase difference; a second frequency division circuit for dividing a frequency of the clock signal according to a second frequency division ratio controlled by the modulation control circuit; and a phase comparison circuit for detecting a phase difference between signals frequency-divided by the first and second frequency division circuits. The second oscillation circuit is configured to variably control the frequency of the clock signal according to the phase difference. The modulation control circuit controls the second frequency division ratio such that a spread spectrum width of the clock signal differs between a low frequency range and a high frequency range with a reference frequency in between. |
