发明名称 IMAGE SCALING PROCESSOR AND IMAGE SCALING PROCESSING METHOD
摘要 An image scaling processor includes: a coefficient computing circuit that calculates interpolation coefficients to be used in an image scaling process; a multiplier that multiplies input image data by the interpolation coefficients provided from the coefficient computing circuit such that the interpolation coefficients respectively correspond to input pixels constituting the input image data; an adder that iteratively adds pieces of multiplied data output from the multiplier and obtains a total sum of the pieces of multiplied data for a predetermined number of the input pixels; a selector that outputs a total sum of the multiplied data at a timing at which the total sum of the pieces of multiplied data is obtained for the predetermined number of the input pixels; and a shift circuit that shifts an output of the selector to adjust a bit count of the output image data to a bit count of the input image data.
申请公布号 US2015086136(A1) 申请公布日期 2015.03.26
申请号 US201414487535 申请日期 2014.09.16
申请人 MegaChips Corporation 发明人 MIZUNO Yusuke
分类号 G06T3/40 主分类号 G06T3/40
代理机构 代理人
主权项 1. An image scaling processor that performs an image scaling process of interpolating pixels of input image data and converting the input image data to U/D times (U and D are natural numbers) as output image data, the processor comprising: a coefficient computing circuit that calculates interpolation coefficients to be used in said image scaling process; a multiplier that multiplies said input image data by said interpolation coefficients provided from said coefficient computing circuit such that said interpolation coefficients respectively correspond to input pixels constituting said input image data; an adder that iteratively adds pieces of multiplied data output from said multiplier and obtains a total sum of said pieces of multiplied data for a predetermined number of said input pixels; a selector that outputs a total sum of said pieces of multiplied data at a timing at which the total sum of said pieces of multiplied data is obtained for the predetermined number of said input pixels; and a shift circuit that shifts an output of said selector to adjust a bit count of said output image data to a bit count of said input image data, wherein said interpolation coefficients calculated by said coefficient computing circuit are converted into integers such that a total sum thereof is equal to 2 raised by a predetermined number.
地址 Osaka-shi JP