| 摘要 |
<p>Proposed is a phase-frequency detector, PFD, circuit suitable for use in a phase lock loop, PLL, circuit. The PFD circuit comprises: a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference; and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.</p> |
